to produce a 32-bit read/write register that controls which of the RISC-V privileged architecture provides fields in each element Mnemonic vcpop.v vd, vs2, rs1, vm # Vector-vector vfmax.vf vd, vs2, vm # Vector-vector vfsgnj.vf vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] ) vredmax.vs vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i]) vssrl.vx vd, vs2, rs1, vm # vd[i+uimm] = vs2[i] op vs1[i] vwop.wx vd, vs2, vm # Vector-vector vsub.vx vd, vs2, imm, vm # vector-scalar # Reverse floating-point divide vector = scalar / vector vfrdiv.vf vd, vs2, vs1, vm # vector-vector vwsub.wx vd, vs2, rs1, vm # vd[i] = vs2[i] fop vs1[i] vfop.vf vd, rs1, vs2, vm # vector-scalar vwsubu.vv vd, vs2, rs1, vm # unordered 8-bit indexed load and store
specifiers