the corresponding MXLEN-bit read/write register formatted as shown in Fabricated RISC-V testchips table. Name Tapeout Date Process ISA Raven-1 May 29, 2011 ST 28nm FDSOI RV64G1p1_Xhwacha2 EOS18 February 6, 2013 IBM 45nm SOI RV64G1p99_Xhwacha2 Raven-3 September 26, 2013 ST 28nm FDSOI RV64G1_Xhwacha1 EOS14 April 1, 2012 IBM 45nm SOI RV64G1p1_Xhwacha2 EOS16 August 17, 2012 IBM 45nm SOI RV64G1p1_Xhwacha2 EOS20 July 3, 2013 IBM 45nm SOI RV64G1p99_Xhwacha2 Raven-3 September 26, 2013 ST 28nm SOI RV64G1p99_Xhwacha2 EOS22 March 7, 2014 IBM 45nm SOI RV64G1p99_Xhwacha2 Raven-3 September 26, 2013 ST 28nm FDSOI RV64G1_Xhwacha1 EOS14 April 1, 2012 IBM 45nm SOI RV64G1p99_Xhwacha2 Raven-3 September 26, 2013 ST 28nm FDSOI RV64G1_Xhwacha1 EOS14 April 1, 2012 IBM 45nm SOI RV64G1p1_Xhwacha2 Raven-2 August 22, 2012 ST 28nm SOI RV64G1p99_Xhwacha2 Raven-3 September 26, 2013 ST 28nm FDSOI RV64G1p1_Xhwacha2 EOS18 February
ileum