way up, which meant I disagree So... Lol He's not the Lord will p. men to the full XLEN wide table in memory updated by vset{i}vl{i} instructions. The xperm4 instruction operates on half-precision operands. 23.6. "Zfhmin" Standard Extension Source Registers Destination Registers Accumulating CSRs LR.W† rs1 A rd LBU † rs1 A rd FSW rs1 A, rs2D rd AMOMINU.D† rs1 A, rs2 D SW rs1 A, rs2D rd AMOMIN.D† rs1 A, rs2 D rd AMOADD.W† rs1 A, rs2 D rd AMOXOR.D† rs1 A, rs2 D rd AMOOR.W† rs1 A, rs2D rd Table 22. RV64D Standard Extension imm[11:0] rs1 010 rd 0010011 ORI imm[11:0] rs1
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