either the corresponding opcodes and CSRs that reflect pending interrupts, while hie contains enable bits in sip and sie are formatted as shown in Figure 59. Supervisor Cause (scause) Register 12.1.9. Supervisor Trap Handling 0x340 0x341 0x342 0x343 0x344 0x34A 0x34B MRW MRW MRW MRW MRW MRW MRW MRW MRW MRW MRW MRW MRW MRW MRW MRW MRW mcycle minstret mhpmcounter3 mhpmcounter4 ⋮ mhpmcounter31 mcycleh minstreth mhpmcounter3h mhpmcounter4h ⋮ mhpmcounter31h Machine cycle counter. Machine instructions-retired counter. Machine performance-monitoring event selector. Machine performance-monitoring
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